This invention relates to high speed CML logic gate systems for providing logic functions, such as AND, OR and XOR.
Several digital systems that provide circuits for generating logic functions, such as AND, OR, NAND, NOR and XOR (EXclusive OR) do so using circuits that are complex and non-symmetrical so that at least two different sub-systems must be fabricated and joined in order to generate one or more of these logic functions. What is needed is a system that uses symmetrical and simpler circuits to generate the logic functions and that has the flexibility to provide other logic functions as well, through change of one or a few input control voltages.
These needs are met by the invention, which provides a single, symmetrical circuit that can be converted to generate (1) AND, NAND, OR and NOR logic functions and (2) XOR and XNOR logic functions by changing the relative voltage levels at one or more of six control input terminals. No other changes are required to switch between generating one type of logic function to generating another type of logic function. Each circuit uses no more than 15 transistors, four resistors and a capacitor and accepts three input control signals and first and second data input signal pairs.